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HT48RA3 8-bit remote type otp mcu block diagram rev. 1.20 1 may 12, 2003 general description this device is an 8-bit high performance risc-like mcu designed for multiple i/o product applications. the de - vice is particularly suitable for use in products such as universal remote controller (urc). a halt feature is in - cluded to reduce power consumption. the data rom can be used to store codes of remote control. features operating voltage: 2.2v~3.6v 23 bidirectional i/o lines (max.) 1 interrupt input shared with an i/o line 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler (tmr0) 16-bit programmable timer/event counter and over - flow interrupts (tmr1) on-chip crystal and rc oscillator watchdog timer 24k 16 program memory eprom (8k 16 bits 3 banks) 224 8 data memory ram pfd supported halt function and wake-up feature reduce power consumption 8-level subroutine nesting up to 1 s instruction cycle with 4mhz system clock at v dd =3v bit manipulation instruction 16-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles 28-pin skdip/sop package

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pin assignment pin description pin name i/o rom code option description res i schmitt trigger reset input, active low. pa0~pa7 i/o wake-up* pull-high*** bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by a option. software instructions determine the cmos output or schmitt trigger input with/without pull-high resistor. the pull-high resistor of each input/output line is also optional. pb0/pfd pb1~pb7 i/o pull-high** pb0 or pfd bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with/without pull-high resis- tor. the pull-high resistor of each input/output line is also optional. the output mode of pb0 can be used as an internal pfd signal output and it can be used as a various frequency carrier signal. vss negative power supply, ground pc0/tmr0 pc1~pc4 pc5/tmr1 i/o pull-high* bidirectional 6-bit input/output port. software instructions determine the cmos output or schmitt trigger input with/without pull-high resis - tor. the pull-high resistor of each input/output line is also optional. pc0 and pc5 are pin shared with tmr0 and tmr1 function pins. pf0/int i/o pull-high* bidirectional 1-bit input/output port. software instructions determine the cmos output or schmitt trigger input with/without pull-high resis - tor. the pull-high resistor of this input/output line is also optional. pf0 is pin shared with the int function pin. vdd positive power supply osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or crystal (determined by option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. note: *: bit option **: nibble option ***: byte option HT48RA3 rev. 1.20 2 may 12, 2003 2 / 3 0 1 4 5 2 / 3 0 4 1 0 3 / 2 5 4 1 - 3 - / $ 1 $ 0 $ 3 $ /

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absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +5.5v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.2 3.6 v i dd operating current 3v no load, f sys =4mhz 35ma i stb1 standby current (wdt enabled) 3v no load, system halt 510 a i stb2 standby current (wdt disabled) 3v no load, system halt 0.1 1 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (res ports) 0 0.4v dd v v ih2 input high voltage (res ports) 0.9v dd v dd v i ol i/o port sink current 3v v ol =0.1v dd 510 ma i oh1 i/o port source current 3v v oh =0.9v dd 2 5 ma i oh2 i/o port source current 3v v oh =0.8v dd 4 8 ma r ph pull-high resistance 3v 40 60 80 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 3v 400 4000 khz f timer timer i/p frequency (tmr0/tmr1) 3v 50% duty 0 4000 khz t wdtosc watchdog oscillator 3v 45 90 180 s t wdt1 watchdog time-out period (wdt osc) 3v without wdt prescaler 11.5 23 46 ms t wdt2 watchdog time-out period (f sys /4) 3v without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period power-up, reset or wake-up from halt 1024 t sys t int interrupt pulse width 1 s t acc data rom access time 1 s note: t sys =1/(f sys ) HT48RA3 rev. 1.20 3 may 12, 2003
functional description HT48RA3 rev. 1.20 4 may 12, 2003 execution flow the system clock for the mcu is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruc - tion cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading register, subroutine call or return from subroutine, initial reset, internal interrupt, external inter - rupt or return from interrupts, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. 4 1 4 1 4 1 ! ) , , 6
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execution flow mode program counter *14~*8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000 00000000 external interrupt 0000000 00000100 timer/event counter 0 overflow 0000000 00001000 timer/event counter 1 overflow 0000000 00001100 skip *14~*13, (*12~*0+2): (within current bank) loading pcl *14~*8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp (5~6), #12~#8 #7 #6 #5 #4 #3 #2 #1 #0 return (ret, reti) s14~s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *14~*0: program counter bits s14~s0: stack register bits #14~#0: instruction code bits @7~@0: pcl bits 1 bank: 8k words
HT48RA3 rev. 1.20 5 may 12, 2003 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 8192 16 bits 3 banks, addressed by the program coun - ter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in - terrupt is enabled and the stack is not full, the program begins execution at location 008h . location 00ch this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter- rupt is enabled and the stack is not full, the program begins execution at location 00ch. table location any location in the program memory can be used as look-up tables. the instructions tabrdc [m] (page specified by tbhp) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the higher-order byte table pointer tbhp (1fh) and lower-order byte table pointer tblp (07h) are read/write registers, which indicate the table locations. before accessing the table, the location has to be placed in tbhp and tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the ta - ble read instruction, the contents of tblh in the main routine are likely to be changed by the table read in - struction used in the isr. errors are thus brought about. given this, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both main routine and the isr, the in - terrupt(s) is supposed to be disabled prior to the table read instruction. it (they) will not be enabled until the tblh in the main routine has been backup. all table related instructions require 2 cycles to complete the operation. stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read- able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack 3 , < # ! 0 = = & > # , # ! # # ? ! # , 8 ! , ! " ! , < ! # # > ! ,
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! , ! " ! , < ! # , program memory instruction table location *14~*8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] tbhp @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1011111 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *14~*0: table location bits @7~@0: table pointer bits
HT48RA3 rev. 1.20 6 may 12, 2003 pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad - dresses are stored). data memory ram the data memory is designed with 250 8 bits. the data memory is divided into two functional groups: special function registers and general purpose data memory (224 8). most are read/write, but some are read only. the special function registers include the indirect ad - dressing registers (r0;00h, r1;02h) bank pointer (bp; 04h), timer/event counter 0 (tmr0;0dh), timer/event counter 0 control register (tmr0c;0eh), timer/event counter 1 higher order byte register (tmr1h;0fh), timer/event counter 1 lower order byte register (tmr1l;10h), timer/event counter 1 control register (tmr1c;11h), program counter lower-order byte register (;06h), memory pointer registers (mp0;01h, mp1;03h), accumulator (;05h), table pointer (tblp;07h, tbhp; 1fh), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register (intc;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h, pf;1ch, and i/o control registers (pac;13h, pbc;15h, pcc;17h, pfc;1dh). the remaining space before the 20h is re- served for future expanded usage and reading these locations will get 00h . the general purpose data memory, addressed from 20h to ffh, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] ([02h]) will access data memory pointed to by mp0 (mp1). reading location 00h (02h) itself indi - rectly will return the result 00h. writing indirectly results in no operation. the memory pointer registers (mp0 and mp1) are 8-bit registers. accumulator the accumulator is closely related to alu operations. it is also mapped to location of the data memory and can carry out immediate data operations. the data move - ment between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) increment and decrement (inc, dec) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. * , " $ $ , 6 1 , - & ! 7 " # , " $ $ , = = = 4 = 1 = 0 = 3 = / = 2 = 5 = $ = - =
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HT48RA3 rev. 1.20 7 may 12, 2003 status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pd), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pd flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pd flag. in addition operations related to the status register may give dif - ferent results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt in - struction. the pd flag can be affected only by execut - ing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control register (intc;0bh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the inter - rupt request will not be acknowledged, even if the re - lated interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre - vented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of the int and the related interrupt request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initial- ized by setting the timer/event counter 0 interrupt re- quest flag (t0f; bit 5 of intc), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further in- terrupts. labels bits function c0 c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared by system power-up or executing the clr wdt instruction. pd is set by exe - cuting the halt instruction. to 5 to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6 unused bit, read as 0 7 unused bit, read as 0 status register
HT48RA3 rev. 1.20 8 may 12, 2003 the internal timer/even counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (t1f;bit 6 of intc), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will oc - cur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an in - terrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. no. interrupt source priority vector a external interrupt 1 04h b timer/event counter 0 overflow 2 08h c timer/event counter 1 overflow 3 0ch the timer/event counter 0/1 interrupt request flag (t0f/t1f), external interrupt request flag (eif), enable timer/event counter 0/1 interrupt bit (et0i/et1i), en- able external interrupt bit (eei) and enable master inter- rupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eei, et0i and et1i are used to control the enabling/dis- abling of interrupts. these bits prevent the requested in- terrupt from being serviced. once the interrupt request flags (t0f, t1f, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. in - terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the original control sequence will be dam - aged once the call operates in the interrupt subrou - tine. oscillator configuration there are 2 oscillator circuits in the mcu. there are 2 oscillator circuits implemented in the mi - cro-controller. both of them are designed for system clocks, namely the rc oscillator and the crystal oscillator, which are de - termined by options. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and resists the external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss is required and the resistance should range from 100k to 820k . the system clock, divided by 4, is available on osc2, which can be used to syn- chronize external logic. the internal rc oscillator pro- vides the most cost effective solution. however, the frequency of oscillation may vary with vdd, tempera - tures and the chip itself due to process variations. it is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase register bit no. label function intc (0bh) 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) 4 eif external interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 6 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc register
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HT48RA3 rev. 1.20 9 may 12, 2003 shift required for the oscillator, and no other external components are demanded. instead of a crystal, the resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external ca - pacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 90 s. the wdt oscillator can be disabled by rom code option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator), instruction clock (system clock divided by 4), determines the rom code option. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be dis - abled by rom code option. if the watchdog timer is dis - abled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 90 s/3v normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 23ms/3v. this time-out period may vary with tempera- tures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.9s/3v seconds. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are re - served for user s defined flags, which can be used to in - dicate some specified status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts register the wdt overflow under normal operation will initialize chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset and only the pc and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res ), software in - struction and a halt instruction. the software instruc - tion include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruc - tion, only one can be active depending on the rom code option clr wdt times selection option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and re - counted again (if the wdt clock is from the wdt os - cillator). all of the i/o ports maintain their original status. the pd flag is set and the to flag is cleared. & ! ,
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HT48RA3 rev. 1.20 10 may 12, 2003 the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pd flags are ex - amined, the reason for chip reset can be determined. the pd flag is cleared by system power-up or executing the clr wdt instruction and is set when executing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the pc and sp; the others remain in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stim - ulus, the program will resume execution of the next in - struction. if it awakens from an interrupt, two sequence may occur. if the related interrupt is disabled or the inter - rupt is enabled but the stack is full, the program will re - sume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt re - sponse takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up func - tion of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the pc and sp, leaving the other cir - cuits in their original state. some registers remain un - changed during other reset conditions. most registers are reset to the initial condition when the reset condi - tions are met. by examining the pd and to flags, the program can distinguish between different chip resets . to pd reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. the functional unit chip reset status are shown below. pc 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode sp points to the top of the stack ! , # 9 !
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reset configuration
HT48RA3 rev. 1.20 11 may 12, 2003 the states of the registers is summarized in the table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pf ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pfc ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown
HT48RA3 rev. 1.20 12 may 12, 2003 timer/event counter two timer/event counters are implemented in the de - vice. the timer/event counter 0 contains an 8-bit pro - grammable count-up counter and the clock may come from an external source or the system clock. the timer/event counter 1 contains an 16-bit programma - ble count-up counter and the clock may come from an external source or the system clock divided by 4. of the two timer/event counters, using external clock in - put allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. while using the internal clock allows the user to generate an accurate time base. only the timer/event counter 0 can generate pfd sig - nal by using external or internal clock, and pfd fre - quency is determine by the equation f int /[2 (256-n)]. there are 2 registers related to timer/event counter 0; tmr0(0dh), tmr0c(0eh). in timer/event counter 0 counting mode (ton=1), writing tmr0 will only put the written data to preload register (8 bits). the timer/event counter 0 preload register is changed by each writing tmr0 operations. reading tmr0 will also latch the tmr0 to the destination. the tmr0c is the timer/event counter 0 control register, which defines the operating mode, counting enable or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr0) pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0). the counting is based on the f int clock. in the event count or timer mode, once the timer/event counter 0 starts counting, it will count from the current contents in the timer/event counter 0 to ffh. once overflow occurs, the counter is reloaded from the timer/event counter 0 preload register and generates the corresponding interrupt request flag (t0f; bit 5 of intc) at the same time. in pulse width measurement mode with the ton and te bits are equal to one, once the tmr0 has received a transition from low to high (or high to low if the te bit is 0) it will start counting until the tmr0 returns to the original level and reset the ton. the measured result will re - main in the timer/event counter 0 even if the activated transition occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transition pulse. note that, in this operat - ing mode, the timer/event counter 0 starts counting not according to the logic level but according to the transi - tion edges. in the case of counter overflows, the counter 0 is reloaded from the timer/event counter 0 preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit(ton; bit 4 of tmr0c) should be set to 1. in the pulse width measurement mode, the ton will be cleared automati - cally after the measurement cycle is complete. but in the other two modes the ton can only be reset by instruc - tions. the overflow of the timer/event counter 0 is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i can disabled the corre - sponding interrupt service. in the case of timer/event counter 0 off condition, writing data to the timer/event counter 0 preload regis - ter will also load the data to timer/event counter 0. but if the timer/event counter 0 is turned on, data written to the timer/event counter 0 will only be kept in the timer/event counter 0 preload register. the timer/event counter 0 will still operate until the overflow occurs (a timer/event counter 0 reloading will occur at the same time). when the timer/event counter 0 (reading tmr0) is read, the clock will be blocked to avoid errors. as this may results in a counting error, this must be taken into consideration by the programmer. the bit 0~2 of the tmr0c can be used to define the pre-scaling stages of the internal clock sources of timer/event counter 0. the definitions are as shown. label (tmr0c) bits function psc0~ psc2 0~2 to define the prescaler stages, psc2, psc1, psc0= 000: f int =f sys /2 001: f int =f sys /4 010: f int =f sys /8 011: f int =f sys /16 100: f int =f sys /32 101: f int =f sys /64 110: f int =f sys /128 111: f int =f sys /256 te 3 to define the tmr0 active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) ton 4 to enable/disable timer 0 counting (0=disabled; 1=enabled) 5 unused bit, read as 0 tm0 tm1 6 7 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c register
HT48RA3 rev. 1.20 13 may 12, 2003 there are 3 registers related to timer/event counter 1; tmr1h(0fh), tmr1l(10h), tmr1c(11h). writing tmr1l will only put the written data to an internal lower-order byte buffer (8 bits) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l preload registers, respectively. the timer/event counter 1 preload register is changed by each writing tmr1h op - erations. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr1c is the timer/event counter 1 control register, which defines the operating mode, counting en - able or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the instruction clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr1). the counting is based on the instruction clock. in the event count or timer mode, once the timer/event counter 1 starts counting, it will count from the current contents in the timer/event counter 1 to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter 1 preload register and generates the corresponding interrupt request flag (t1f; bit 6 of intc) at the same time. in pulse width measurement mode with the ton and te bits are equal to one, once the tmr1 has received a transition from low to high (or high to low if the te bit is 0) it will start counting until the tmr1 returns to the original level and reset the ton. the measured result will re - main in the timer/event counter 1 even if the activated transition occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transition pulse. note that, in this operat - ing mode, the timer/event counter 1 starts counting not according to the logic level but according to the transi - tion edges. in the case of counter overflows, the counter 1 is reloaded from the timer/event counter 1 preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit(ton; bit 4 of tmr1c) should be set to 1. in the pulse width measurement mode, the ton will be cleared automati - cally after the measurement cycle is complete. but in the other two modes the ton can only be reset by instruc - tions. the overflow of the timer/event counter 1 is one of the wake-up sources. no matter what the operation mode is, writin ga0to et1i can disabled the corre - sponding interrupt service. in the case of timer/event counter 1 off condition, writing data to the timer/event counter 1 preload regis- ter will also load the data to timer/event counter 1. but if the timer/event counter 1 is turned on, data written to the timer/event counter 1 will only be kept in the , + # ' ! ) ! ' ,
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HT48RA3 rev. 1.20 14 may 12, 2003 timer/event counter 1 preload register. the timer/event counter 1 will still operate until the overflow occurs (a timer/event counter 1 reloading will occur at the same time). when the timer/event counter 1 (reading tmr1h) is read, the clock will be blocked to avoid errors. as this may results in a counting error, this must be taken into consideration by the programmer. the definitions of the tmr1c are as shown. label (tmr1c) bits function 0~2 unused bit, read as 0 te 3 to define the active edge of tmr1 pin input signal (0/1: active on low to high/high to low) ton 4 to enable/disable timer 1 counting (0/1: disabled/enabled) 5 unused bit, read as 0 tm0 tm1 6 7 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c register input/output ports there are 23 bi-directional input/output lines in the mi- cro-controller, labeled from pa to pc and pf, which are mapped to the data memory of [12h], [14h], [16h] and [1ch], respectively. all of these i/o ports can be used as input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m = 12h, 14h, 16h or 1ch). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pfc) to control the input/output configuration. with this control register, cmos output or schmitt trig - ger input with or without (depends on options) pull-high resistor structures can be reconfigured dynamically (i.e., on-the fly) under software control. to function as an in - put, the corresponding latch of the control register has to be set as 1 . the pull-high resistor (if the pull-high re - sistor is enabled) will be exhibited automatically. the in - put sources also depends on the control register. if the control register bit is 1 , the input will read the pad state ( mov and read-modify-write instructions ). if the con - trol register bit is 0, the contents of the latches will move to internal data bus ( mov and read-modify-write in - structions). the input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h and 1dh. $ . $ / - - . - /
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HT48RA3 rev. 1.20 15 may 12, 2003 after a chip reset, these input/output lines stay at high levels (pull-high options) or floating state (non-pull-high options). each bit of these input/output latches can be set or cleared by set [m].i (m = 12h, 14h, 16h or 1ch) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. the highest 2 bits of port c and 7 bits of port f are not physically implemented; on reading them a 0 is returned whereas writing then results in a no-operation. pull-high resistors of each port are decided by a option bit. the pb0 is pin-shared with pfd signal, respectively. if the pfd option is selected, the output signal in output mode of pb0 will be the pfd signal. the input mode al - ways remain its original functions. the pf0 and pc0 are pin-shared with int and tmr0. the int signal is di - rectly connected to pf0. the pfd output signal (in out - put mode) are controlled by the pb0 data register only. the truth table of pb0/pfd is listed below. the truth table of pb0/pfd is as shown. pbc (15h) bit0 i o o o pb0/pfd option x pb0 pfd pfd pb0 (14h) bit0 x d 0 1 pb0 pad status i d 0 pfd note: i: input; o: output; d: data bank pointer there is a bank pointer used to control the program flow to go to any banks. a bank contains 8k 16 address space. the contents of bank pointer are load into pro - gram counter when the jmp or call instruction is exe - cuted. the program counter is a 15-bit register whose contents are used to specify the executed instruction addresses. when calling a subroutine or an interrupt event occur - ring, the contents of the program counter are save into stack registers. if a returning from subroutine occurs, the contents of the program counter will restore from stack registers. options the following table shows all kinds of code option in the mcu. all of the mask options must be defined to ensure proper system functioning. function pa0~pa7 wake-up enable or disable options pc pull-high enable or disable pa pull-high enable or disable: byte option pf pull-high enable or disable pb pull-high (pb0~pb3, pb4~pb7) enable or disable: nibble option pb0 or pfd clr wdt instructions system oscillators: rc or crystal wdt enable or disable wdt clock source: wdtosc or system clock/4
application circuits note: if 400khzHT48RA3 rev. 1.20 16 may 12, 2003 " , ' # f ; f f ; f

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instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none HT48RA3 rev. 1.20 17 may 12, 2003
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to (4) ,pd (4) to (4) ,pd (4) none none to,pd note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pd are cleared. otherwise the to and pd flags remain unchanged. HT48RA3 rev. 1.20 18 may 12, 2003
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) tc2 tc1 to pd ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 19 may 12, 2003
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 20 may 12, 2003
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pd) and time-out bit (to) are cleared. operation wdt 00h pd and to 0 affected flag(s) tc2 tc1 to pd ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 21 may 12, 2003
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 22 may 12, 2003
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pd 1 to 0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 23 may 12, 2003
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) tc2 tc1 to pd ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) tc2 tc1 to pd ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 24 may 12, 2003
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) tc2 tc1 to pd ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 25 may 12, 2003
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 26 may 12, 2003
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 27 may 12, 2003
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) tc2 tc1 to pd ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 28 may 12, 2003
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 29 may 12, 2003
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh
code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 30 may 12, 2003
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) tc2 tc1 to pd ov z ac c HT48RA3 rev. 1.20 31 may 12, 2003
package information 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 330 375 0 15 HT48RA3 rev. 1.20 32 may 12, 2003 , , 2 0 1 $ -
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28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 HT48RA3 rev. 1.20 33 may 12, 2003 2 0 1 $ -

g * =
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 HT48RA3 rev. 1.20 34 may 12, 2003 $
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carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 HT48RA3 rev. 1.20 35 may 12, 2003 + ! % - $

HT48RA3 rev. 1.20 36 may 12, 2003 copyright 2003 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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